134 lines
4.9 KiB
C
134 lines
4.9 KiB
C
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/****************************************************************
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* *
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* Copyright 2001, 2002 Sanchez Computer Associates, Inc. *
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* *
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* This source code contains the intellectual property *
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* of its copyright holder(s), and is made available *
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* under a license. If you do not know the terms of *
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* the license, please stop and do not read further. *
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* *
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****************************************************************/
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/* axp.h - AXP machine instruction information.
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*
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* Requires "axp_registers.h" and "axp_gtm_registers.h".
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*
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*/
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/* Machine instruction templates. */
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#define ALPHA_INS_ADDL ((unsigned)0x10 << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BEQ ((unsigned)0x39 << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BGE ((unsigned)0x3e << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BGT ((unsigned)0x3f << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BIS ((unsigned)0x11 << ALPHA_SHIFT_OP | 0x20 << ALPHA_SHIFT_FUNC)
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#define ALPHA_INS_BLE ((unsigned)0x3b << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BLT ((unsigned)0x3a << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BLBC ((unsigned)0x38 << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BLBS ((unsigned)0x3c << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BNE ((unsigned)0x3d << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BSR ((unsigned)0x34 << ALPHA_SHIFT_OP)
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#define ALPHA_INS_BR ((unsigned)0x30 << ALPHA_SHIFT_OP)
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#define ALPHA_INS_JMP ((unsigned)0x1a << ALPHA_SHIFT_OP)
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#define ALPHA_INS_JSR ((unsigned)0x1a << ALPHA_SHIFT_OP | 1 << ALPHA_SHIFT_BRANCH_FUNC)
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#define ALPHA_INS_LDA ((unsigned)0x08 << ALPHA_SHIFT_OP)
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#define ALPHA_INS_LDAH ((unsigned)0x09 << ALPHA_SHIFT_OP)
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#define ALPHA_INS_LDL ((unsigned)0x28 << ALPHA_SHIFT_OP)
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#define ALPHA_INS_LDQ ((unsigned)0x29 << ALPHA_SHIFT_OP)
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#define ALPHA_INS_RET ((unsigned)0x1a << ALPHA_SHIFT_OP | 2 << ALPHA_SHIFT_BRANCH_FUNC)
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#define ALPHA_INS_STL ((unsigned)0x2c << ALPHA_SHIFT_OP)
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#define ALPHA_INS_STQ ((unsigned)0x2d << ALPHA_SHIFT_OP)
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#define ALPHA_INS_SUBL ((unsigned)0x10 << ALPHA_SHIFT_OP | 0x9 << ALPHA_SHIFT_FUNC)
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#define ALPHA_INS_SUBQ ((unsigned)0x10 << ALPHA_SHIFT_OP | 0x29 << ALPHA_SHIFT_FUNC)
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/* Bit offsets to instruction fields. */
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#define ALPHA_SHIFT_OP 26
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#define ALPHA_SHIFT_BRANCH_FUNC 14
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#define ALPHA_SHIFT_FUNC 5
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#define ALPHA_SHIFT_LITERAL 13
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#define ALPHA_SHIFT_RA 21
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#define ALPHA_SHIFT_RB 16
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#define ALPHA_SHIFT_RC 0
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#define ALPHA_SHIFT_BRANCH_DISP 0
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#define ALPHA_SHIFT_DISP 0
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/* Bit masks for instruction fields. */
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#define ALPHA_BIT_LITERAL (1 << 12)
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#define ALPHA_MASK_BRANCH_DISP 0x1fffff
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#define ALPHA_MASK_BRANCH_FUNC 0xc00000
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#define ALPHA_MASK_DISP 0xffff
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#define ALPHA_MASK_FUNC 0x7f
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#define ALPHA_MASK_LITERAL 0xff
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#define ALPHA_MASK_OP 0x3f
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#define ALPHA_MASK_REG 0x1f
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/* Alternative assembler mnemonics for machine instruction. */
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#define ALPHA_INS_CLRQ (ALPHA_INS_BIS \
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| (ALPHA_REG_ZERO << ALPHA_SHIFT_RA) \
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| (ALPHA_REG_ZERO << ALPHA_SHIFT_RB))
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#define ALPHA_INS_LPC (ALPHA_INS_BR \
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| (GTM_REG_CODEGEN_TEMP << ALPHA_SHIFT_RA))
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#define ALPHA_INS_MOVE (ALPHA_INS_BIS \
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| ALPHA_REG_ZERO << ALPHA_SHIFT_RB)
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#define ALPHA_INS_NOP (ALPHA_INS_BIS \
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| (ALPHA_REG_ZERO << ALPHA_SHIFT_RA) \
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| (ALPHA_REG_ZERO << ALPHA_SHIFT_RB) \
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| (ALPHA_REG_ZERO << ALPHA_SHIFT_RC))
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/* Construction forms. */
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#define ALPHA_BRA(op,ra,disp) ((op) | ((ra) << ALPHA_SHIFT_RA) | (disp)&ALPHA_MASK_BRANCH_DISP)
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#define ALPHA_JMP(op,ra,rb) ((op) | ((ra) << ALPHA_SHIFT_RA) | ((rb) << ALPHA_SHIFT_RB))
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#define ALPHA_LIT(op,ra,lit,rc) ((op) | ((ra) << ALPHA_SHIFT_RA) \
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| (((lit)&ALPHA_MASK_LITERAL) << ALPHA_SHIFT_LITERAL) \
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| ALPHA_BIT_LITERAL \
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| ((rc) << ALPHA_SHIFT_RC))
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#define ALPHA_MEM(op,ra,rb,disp)((op) | ((ra) << ALPHA_SHIFT_RA) | ((rb) << ALPHA_SHIFT_RB) | (disp)&ALPHA_MASK_DISP)
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#define ALPHA_OPR(op,ra,rb,rc) ((op) | ((ra) << ALPHA_SHIFT_RA) | ((rb) << ALPHA_SHIFT_RB) | ((rc) << ALPHA_SHIFT_RC))
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#ifdef DEBUG
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#define GET_OPCODE(ains) ((ains >> ALPHA_SHIFT_OP) & ALPHA_MASK_OP)
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#define GET_RA(ains) ((ains >> ALPHA_SHIFT_RA) & ALPHA_MASK_REG)
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#define GET_RB(ains) ((ains >> ALPHA_SHIFT_RB) & ALPHA_MASK_REG)
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#define GET_RC(ains) ((ains >> ALPHA_SHIFT_RC) & ALPHA_MASK_REG)
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#define GET_MEMDISP(ains) ((ains >> ALPHA_SHIFT_DISP) & ALPHA_MASK_DISP)
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#define GET_BRDISP(ains) ((ains >> ALPHA_SHIFT_BRANCH_DISP) & ALPHA_MASK_BRANCH_DISP)
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#define GET_FUNC(ains) ((ains >> ALPHA_SHIFT_FUNC) & ALPHA_MASK_FUNC)
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#define ADDL_INST "addl"
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#define SUBL_INST "subl"
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#define SUBQ_INST "subq"
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#define BIS_INST "bis"
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#define JSR_INST "jsr"
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#define RET_INST "ret"
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#define JMP_INST "jmp"
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#define LDA_INST "lda"
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#define LDAH_INST "ldah"
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#define LDL_INST "ldl"
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#define LDQ_INST "ldq"
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#define STL_INST "stl"
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#define STQ_INST "stq"
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#define BR_INST "br"
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#define BSR_INST "bsr"
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#define BLBC_INST "blbc"
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#define BEQ_INST "beq"
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#define BLT_INST "blt"
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#define BLE_INST "ble"
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#define BLBS_INST "blbs"
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#define BNE_INST "bne"
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#define BGE_INST "bge"
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#define BGT_INST "bgt"
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#define CONSTANT "Constant 0x"
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/* Space for op_code to be in */
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#define OPSPC 7
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#endif
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