207 lines
10 KiB
C
207 lines
10 KiB
C
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/****************************************************************
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* *
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* Copyright 2003, 2009 Fidelity Information Services, Inc *
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* *
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* This source code contains the intellectual property *
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* of its copyright holder(s), and is made available *
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* under a license. If you do not know the terms of *
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* the license, please stop and do not read further. *
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* *
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****************************************************************/
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#ifndef EMIT_CODE_SP_INCLUDED
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#define EMIT_CODE_SP_INCLUDED
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#include "axp_registers.h"
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#include "axp_gtm_registers.h"
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#include "axp.h"
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void emit_base_offset(int base, int offset);
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int alpha_adjusted_upper(int offset);
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#ifdef DEBUG
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void format_machine_inst(void);
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void fmt_ra(void);
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void fmt_ra_rb(void);
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void fmt_ra_rb_rc(void);
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void fmt_ra_mem(void);
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void fmt_ra_brdisp(void);
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#endif
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#define INST_SIZE (int)SIZEOF(uint4)
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#define BRANCH_OFFSET_FROM_IDX(idx_start, idx_end) (idx_end - (idx_start + 1))
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#define LONG_JUMP_OFFSET (0x4ffffffc) /* should be large enough to force the long jump instruction sequence */
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#define MAX_BRANCH_CODEGEN_SIZE 32 /* The length in bytes, of the longest form of branch instruction sequence */
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#define MAX_OFFSET 0x3fff
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#define STACK_ARG_OFFSET(indx) (8 * (indx)) /* All arguments on Alpha platforms are 8 bytes wide on stack */
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#define MACHINE_FIRST_ARG_REG ALPHA_REG_A0
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/* Register usage in some of the code generation expansions */
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#define CALLS_TINT_TEMP_REG ALPHA_REG_R1
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#define CLRL_REG ALPHA_REG_ZERO
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#define CMPL_TEMP_REG ALPHA_REG_T1
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#define GET_ARG_REG(indx) (ALPHA_REG_A0 + (indx))
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#define MOVC3_SRC_REG ALPHA_REG_R0
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#define MOVC3_TRG_REG ALPHA_REG_R1
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#define MOVL_RETVAL_REG ALPHA_REG_V0
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#define MOVL_REG_R1 ALPHA_REG_R1
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/* Macros to define the opcodes for use in emit_jmp() and emit_tip() args */
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#define GENERIC_OPCODE_BEQ ((uint4)ALPHA_INS_BEQ)
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#define GENERIC_OPCODE_BGE ((uint4)ALPHA_INS_BGE)
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#define GENERIC_OPCODE_BGT ((uint4)ALPHA_INS_BGT)
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#define GENERIC_OPCODE_BLE ((uint4)ALPHA_INS_BLE)
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#define GENERIC_OPCODE_BLT ((uint4)ALPHA_INS_BLT)
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#define GENERIC_OPCODE_BNE ((uint4)ALPHA_INS_BNE)
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#define GENERIC_OPCODE_BLBC ((uint4)ALPHA_INS_BLBC)
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#define GENERIC_OPCODE_BLBS ((uint4)ALPHA_INS_BLBS)
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#define GENERIC_OPCODE_BR ((uint4)ALPHA_INS_BR)
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#define GENERIC_OPCODE_LDA ((uint4)ALPHA_INS_LDA)
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#define GENERIC_OPCODE_LOAD ((uint4)ALPHA_INS_LDL)
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#define GENERIC_OPCODE_STORE ((uint4)ALPHA_INS_STL)
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#define GENERIC_OPCODE_NOP ((uint4)ALPHA_INS_NOP)
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/* Macro to extract parts of generic opcodes */
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#define GENXCT_LOAD_SRCREG(inst) ((inst >> ALPHA_SHIFT_RB) & ALPHA_MASK_REG)
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/* Macros to create specific generated code sequences */
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/* Note that the GEN_CLEAR/SET_TRUTH macros are only used on VMS (TRUTH_IN_REG) */
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#define GEN_CLEAR_TRUTH code_buf[code_idx++] = (ALPHA_INS_STL | ALPHA_REG_ZERO << ALPHA_SHIFT_RA \
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| GTM_REG_DOLLAR_TRUTH << ALPHA_SHIFT_RB \
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| 0 << ALPHA_SHIFT_DISP)
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#define GEN_SET_TRUTH { \
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code_buf[code_idx++] = (ALPHA_INS_BIS | ALPHA_REG_ZERO << ALPHA_SHIFT_RA \
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| 1 << ALPHA_SHIFT_LITERAL | ALPHA_BIT_LITERAL \
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| GTM_REG_CODEGEN_TEMP << ALPHA_SHIFT_RC); \
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code_buf[code_idx++] = (ALPHA_INS_STL | GTM_REG_CODEGEN_TEMP << ALPHA_SHIFT_RA \
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| GTM_REG_DOLLAR_TRUTH << ALPHA_SHIFT_RB \
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| 0 << ALPHA_SHIFT_DISP); \
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}
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#define GEN_LOAD_ADDR(reg, breg, disp) code_buf[code_idx++] = (ALPHA_INS_LDA | reg << ALPHA_SHIFT_RA \
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| breg << ALPHA_SHIFT_RB \
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| (disp & ALPHA_MASK_DISP) << ALPHA_SHIFT_DISP)
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#define GEN_LOAD_WORD(reg, breg, disp) code_buf[code_idx++] = (ALPHA_INS_LDL | reg << ALPHA_SHIFT_RA \
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| breg << ALPHA_SHIFT_RB \
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| (disp & ALPHA_MASK_DISP) << ALPHA_SHIFT_DISP)
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#define GEN_STORE_WORD(reg, breg, disp) code_buf[code_idx++] = (ALPHA_INS_STL | reg << ALPHA_SHIFT_RA \
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| breg << ALPHA_SHIFT_RB \
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| (disp & ALPHA_MASK_DISP) << ALPHA_SHIFT_DISP)
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#define GEN_LOAD_IMMED(reg, disp) GEN_LOAD_ADDR(reg, ALPHA_REG_ZERO, disp)
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#define GEN_CLEAR_WORD_EMIT(reg) emit_trip(*(fst_opr + *inst++), TRUE, ALPHA_INS_STL, reg)
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#define GEN_LOAD_WORD_EMIT(reg) emit_trip(*(fst_opr + *inst++), TRUE, ALPHA_INS_LDL, reg)
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#define GEN_SUBTRACT_REGS(src1, src2, trgt) \
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code_buf[code_idx++] = (ALPHA_INS_SUBL \
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| src1 << ALPHA_SHIFT_RA \
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| src2 << ALPHA_SHIFT_RB \
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| trgt << ALPHA_SHIFT_RC)
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#define GEN_ADD_IMMED(reg, imval) code_buf[code_idx++] = (ALPHA_INS_ADDL \
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| reg << ALPHA_SHIFT_RA \
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| imval << ALPHA_SHIFT_LITERAL | ALPHA_BIT_LITERAL \
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| reg << ALPHA_SHIFT_RC)
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#define GEN_JUMP_REG(reg) code_buf[code_idx++] = (ALPHA_INS_JMP | ALPHA_REG_ZERO << ALPHA_SHIFT_RA \
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| reg << ALPHA_SHIFT_RB)
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#define GEN_STORE_ARG(reg, offset) code_buf[code_idx++] = (ALPHA_INS_STQ | reg << ALPHA_SHIFT_RA \
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| ALPHA_REG_SP << ALPHA_SHIFT_RB \
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| (offset & ALPHA_MASK_DISP) << ALPHA_SHIFT_DISP)
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#define GEN_PCREL code_buf[code_idx++] = (ALPHA_INS_LPC)
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#define GEN_MOVE_REG(trg, src) code_buf[code_idx++] = (ALPHA_INS_MOVE | src << ALPHA_SHIFT_RA | trg << ALPHA_SHIFT_RC)
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#if defined(__vms)
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/* CALL_INST_SIZE is the byte length of the minimum-length instruction sequence to implement a transfer
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* table call. In the case of OpenVMS AXP, this is the sequence:
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*
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* ldl r27, xfer(r11) ; get address of procedure descriptor from transfer table
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* ldq r26, 8(r27) ; get code address of procedure from procedure descriptor
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* jmp r26, (r26) ; call it
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*
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* This value is used to determine how to adjust the offset value for a relative call and may not
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* be appropriate for the Alpha because VAX relative calls are emulated on the Alpha differently.
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*/
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# define CALL_INST_SIZE (3 * INST_SIZE)
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# define GEN_XFER_TBL_CALL(xfer) \
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{ \
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emit_base_offset(GTM_REG_XFER_TABLE, xfer); \
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code_buf[code_idx++] |= ALPHA_INS_LDL | ALPHA_REG_PV << ALPHA_SHIFT_RA; \
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emit_base_offset(ALPHA_REG_PV, 8); \
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code_buf[code_idx++] |= ALPHA_INS_LDQ | ALPHA_REG_RA << ALPHA_SHIFT_RA; \
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code_buf[code_idx++] = ALPHA_INS_JSR | ALPHA_REG_RA << ALPHA_SHIFT_RA | ALPHA_REG_RA << ALPHA_SHIFT_RB; \
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}
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#elif defined(__osf__)
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/* CALL_INST_SIZE is the byte length of the minimum-length instruction sequence to implement a transfer
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* table call. In the case of OSF/1 (Digital Unix) AXP, this is the sequence:
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*
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* ldl r27, offset(r12) # get address of entry point from transfer table
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* jmp r26, (r27) # call it
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*
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* This value is used to determine how to adjust the offset value for a relative call and may not
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* be appropriate for the Alpha because VAX relative calls are emulated on the Alpha differently.
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*/
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# define CALL_INST_SIZE (2 * INST_SIZE)
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# define GEN_XFER_TBL_CALL(xfer) \
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{ \
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emit_base_offset(GTM_REG_XFER_TABLE, xfer); \
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code_buf[code_idx++] |= ALPHA_INS_LDL | ALPHA_REG_PV << ALPHA_SHIFT_RA; \
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code_buf[code_idx++] = ALPHA_INS_JSR | ALPHA_REG_RA << ALPHA_SHIFT_RA | ALPHA_REG_PV << ALPHA_SHIFT_RB; \
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}
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#else
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# error "Unsupported platform"
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#endif
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/* Macros to return an instruction value. This is typcically used to modify an instruction
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that is already in the instruction buffer such as the last instruction that was created
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by emit_pcrel().
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*/
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#define IGEN_COND_BRANCH_REG_OFFSET(opcode, reg, disp) (opcode | ((reg & ALPHA_MASK_REG) << ALPHA_SHIFT_RA) \
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| ((disp & ALPHA_MASK_DISP) << ALPHA_SHIFT_BRANCH_DISP))
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#define IGEN_UCOND_BRANCH_REG_OFFSET(opcode, reg, disp) IGEN_COND_BRANCH_REG_OFFSET(opcode, reg, disp)
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#define IGEN_LOAD_ADDR_REG(reg) (ALPHA_INS_LDA | (reg & ALPHA_MASK_REG) << ALPHA_SHIFT_RA)
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#define IGEN_LOAD_WORD_REG(reg) (ALPHA_INS_LDL | (reg & ALPHA_MASK_REG) << ALPHA_SHIFT_RA)
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#define IGEN_LOAD_NATIVE_REG(reg) IGEN_LOAD_WORD_REG(reg)
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#define IGEN_COND_BRANCH_OFFSET(disp) ((disp & ALPHA_MASK_BRANCH_DISP) << ALPHA_SHIFT_BRANCH_DISP)
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#define IGEN_UCOND_BRANCH_OFFSET(disp) IGEN_COND_BRANCH_OFFSET(disp)
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#define IGEN_LOAD_LINKAGE(reg) (ALPHA_INS_LDQ | (reg & ALPHA_MASK_REG) << ALPHA_SHIFT_RA)
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#define IGEN_GENERIC_REG(opcode, reg) (opcode | ((reg & ALPHA_MASK_REG) << ALPHA_SHIFT_RA))
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/* Some macros that are used in certain routines in emit_code.c. The names of these
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macros start with the routine name they are used in.
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*/
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/* Branch has origin of +1 instructions. However, if the branch was nullified in an earlier shrink_trips,
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* the origin is the current instruction itself */
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#define EMIT_JMP_ADJUST_BRANCH_OFFSET branch_offset = ((branch_offset != 0) ? branch_offset - 1 : 0)
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/* Can jump be done within range of immediate operand */
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#define EMIT_JMP_SHORT_CODE_CHECK (branch_offset >= (-(ALPHA_MASK_BRANCH_DISP/2) - 1) \
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&& branch_offset <= (ALPHA_MASK_BRANCH_DISP/2))
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/* Emit the short jump */
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#define EMIT_JMP_SHORT_CODE_GEN \
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{ \
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code_buf[code_idx++] = (branchop | (reg << ALPHA_SHIFT_RA) \
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| ((branch_offset & ALPHA_MASK_BRANCH_DISP) << ALPHA_SHIFT_BRANCH_DISP)); \
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branch_offset--; \
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}
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/* Is this a conditional branch? */
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#define EMIT_JMP_OPPOSITE_BR_CHECK (branchop != ALPHA_INS_BR && (branchop != ALPHA_INS_BEQ || reg != ALPHA_REG_ZERO))
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#define EMIT_JMP_GEN_COMPARE /* No compare necessary */
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#define EMIT_JMP_LONG_CODE_CHECK FALSE
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/* Is the offset field in this instruction zero? */
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#define EMIT_JMP_ZERO_DISP_COND (0 == ((code_buf[code_idx] >> ALPHA_SHIFT_DISP) & ALPHA_MASK_DISP))
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/* Emit code to load a given numeric literal */
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#define EMIT_TRIP_ILIT_GEN { /* Emit liternal number */ \
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emit_base_offset(ALPHA_REG_ZERO, immediate); \
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code_buf[code_idx++] |= (ALPHA_INS_LDA | \
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(trg_reg & ALPHA_MASK_REG) << ALPHA_SHIFT_RA); \
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}
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/*
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* GT.M on AIX and SPARC is 64bit
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* By default the loads/stores use ldd/std(load double),
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* but if the value being dealt with is a word,the
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* opcode in generic_inst is changed to ldw/stw
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*/
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#define REVERT_GENERICINST_TO_WORD(inst)
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#endif
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