2012-02-05 11:35:58 -05:00
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#################################################################
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# #
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2024-07-19 11:43:27 -04:00
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# Copyright 2007, 2012 Fidelity Information Services, Inc #
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2012-02-05 11:35:58 -05:00
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# #
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# This source code contains the intellectual property #
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# of its copyright holder(s), and is made available #
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# under a license. If you do not know the terms of #
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# the license, please stop and do not read further. #
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# #
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#################################################################
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# PAGE ,132
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.title op_forloop.s
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# .386
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# .MODEL FLAT, C
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.include "g_msf.si"
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.include "linkage.si"
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.INCLUDE "mval_def.si"
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.sbttl op_forloop
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# PAGE +
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# Called with the stack contents:
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# call return
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# ptr to index mval
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# ptr to step mval
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# ptr to terminator mval
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# loop address
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.DATA
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.extern frame_pointer
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ten_dd:
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.long 10
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.text
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.extern add_mvals
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.extern numcmp
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.extern s2n
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loop = 32
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term = 24
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step = 16
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indx = 8
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# PUBLIC op_forloop
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ENTRY op_forloop
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movq frame_pointer(REG_IP),REG64_SCRATCH1
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popq msf_mpc_off(REG64_SCRATCH1)
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#Push the arguments on stack Argument registers are used in intermediate logic
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pushq REG64_ARG3 #loop address. Return address
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pushq REG64_ARG2
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pushq REG64_ARG1
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pushq REG64_ARG0
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enter $0, $0 #rbp pushed on stack and then rbp = rsp
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pushq REG_XFER_TABLE
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movq indx(REG_FRAME_POINTER),REG64_ARG1
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2024-07-19 11:43:27 -04:00
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mv_force_defined_strict REG64_ARG1, l0 # disregard NOUNDEF
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2012-02-05 11:35:58 -05:00
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movq REG64_ARG1, indx(REG_FRAME_POINTER)
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mv_force_num REG64_ARG1, l1
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movq indx(REG_FRAME_POINTER),REG64_ARG1
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movq step(REG_FRAME_POINTER),REG64_ARG0
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movw mval_w_mvtype(REG64_ARG1),REG16_ACCUM
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movw mval_w_mvtype(REG64_ARG0),REG16_ARG2
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andw REG16_ARG2,REG16_ACCUM
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testw $mval_m_int_without_nm,REG16_ACCUM
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je L66
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movl mval_l_m1(REG64_ARG1),REG32_ACCUM
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addl mval_l_m1(REG64_ARG0),REG32_ACCUM
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cmpl $MANT_HI,REG32_ACCUM
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jge L68
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cmpl $-MANT_HI,REG32_ACCUM
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jle L67
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movw $mval_m_int,mval_w_mvtype(REG64_ARG1)
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movl REG32_ACCUM,mval_l_m1(REG64_ARG1)
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jmp L63
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L67: movb $mval_esign_mask,mval_b_exp(REG64_ARG1) #set sign bit
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negl REG32_ACCUM
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jmp L69
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L68: movb $0,mval_b_exp(REG64_ARG1) # clear sign bit
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L69: movw $mval_m_nm,mval_w_mvtype(REG64_ARG1)
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orb $69,mval_b_exp(REG64_ARG1) # set exponent field
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movl REG32_ACCUM,REG32_SCRATCH1
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movl $0,REG32_ARG2
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idivl ten_dd(REG_IP),REG32_ACCUM
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movl REG32_ACCUM,mval_l_m1(REG64_ARG1)
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imull $10,REG32_ACCUM,REG32_ACCUM
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subl REG32_ACCUM,REG32_SCRATCH1
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imull $MANT_LO,REG32_SCRATCH1,REG32_SCRATCH1
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movl REG32_SCRATCH1,mval_l_m0(REG64_ARG1)
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jmp L63
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L66: movq REG64_ARG1,REG64_ARG3
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movl $0,REG32_ARG2
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movq REG64_ARG0,REG64_ARG1
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movq REG64_ARG3,REG64_ARG0
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call add_mvals
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movq indx(REG_FRAME_POINTER),REG64_ARG1
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L63: movq step(REG_FRAME_POINTER),REG64_ARG0
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testw $mval_m_int_without_nm,mval_w_mvtype(REG64_ARG0)
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jne a
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cmpb $0,mval_b_exp(REG64_ARG0)
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jl b
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jmp a2
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a: cmpl $0,mval_l_m1(REG64_ARG0)
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jl b
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a2: movq term(REG_FRAME_POINTER),REG64_ARG0
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jmp e
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b: movq REG64_ARG1,REG64_ARG0 # if step is negative, reverse compare
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movq term(REG_FRAME_POINTER),REG64_ARG1
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e: # compare indx and term
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movw mval_w_mvtype(REG64_ARG1),REG16_ACCUM
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movw mval_w_mvtype(REG64_ARG0),REG16_ARG2
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andw REG16_ARG2,REG16_ACCUM
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testw $2,REG16_ACCUM
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je ccmp
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movl mval_l_m1(REG64_ARG1),REG32_ACCUM
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subl mval_l_m1(REG64_ARG0),REG32_ACCUM
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jmp tcmp
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ccmp: xchgq REG64_ARG0,REG64_ARG1
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call numcmp
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cmpl $0,REG32_ACCUM
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tcmp: jle d
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movq indx(REG_FRAME_POINTER),REG64_ARG1
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movq step(REG_FRAME_POINTER),REG64_ARG0
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movw mval_w_mvtype(REG64_ARG1),REG16_ACCUM
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movw mval_w_mvtype(REG64_ARG0),REG16_ARG2
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andw REG16_ARG2,REG16_ACCUM
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testw $mval_m_int_without_nm,REG16_ACCUM
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je l66
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movl mval_l_m1(REG64_ARG1),REG32_ACCUM
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subl mval_l_m1(REG64_ARG0),REG32_ACCUM
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cmpl $MANT_HI,REG32_ACCUM
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jge l68
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cmpl $-MANT_HI,REG32_ACCUM
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jle l67
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movw $mval_m_int,mval_w_mvtype(REG64_ARG1)
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movl REG32_ACCUM,mval_l_m1(REG64_ARG1)
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jmp l63
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l67: movb $mval_esign_mask,mval_b_exp(REG64_ARG1) # set sign bit
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negl REG32_ACCUM
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jmp l69
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l68: movb $0,mval_b_exp(REG64_ARG1) # clear sign bit
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l69: movw $mval_m_nm,mval_w_mvtype(REG64_ARG1)
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orb $69,mval_b_exp(REG64_ARG1)
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movl REG32_ACCUM,REG32_SCRATCH1
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movl $0,REG32_ARG2 #set edx to 0 before div
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idivl ten_dd(REG_IP),REG32_ACCUM
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movl REG32_ACCUM,mval_l_m1(REG64_ARG1)
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imull $10,REG32_ACCUM,REG32_ACCUM
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subl REG32_ACCUM,REG32_SCRATCH1
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imull $MANT_LO,REG32_SCRATCH1,REG32_SCRATCH1
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movl REG32_SCRATCH1,mval_l_m0(REG64_ARG1)
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jmp l63
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l66: movq REG64_ARG1,REG64_ARG3
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movl $1,REG32_ARG2
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movq REG64_ARG0,REG64_ARG1
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movq REG64_ARG3,REG64_ARG0 #First and fourth args are same
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call add_mvals
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l63: popq REG_XFER_TABLE
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leave
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addq $32,REG_SP #Pop all incoming arguments
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movq frame_pointer(REG_IP),REG64_SCRATCH1
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pushq msf_mpc_off(REG64_SCRATCH1)
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ret
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d: popq REG_XFER_TABLE
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leave
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addq $24,REG_SP #Pop all the arguments except loop address
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ret
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# op_forloop ENDP
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# END
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