503 lines
14 KiB
C
503 lines
14 KiB
C
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/****************************************************************
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* *
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* Copyright 2007, 2009 Fidelity Information Services, Inc *
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* *
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* This source code contains the intellectual property *
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* of its copyright holder(s), and is made available *
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* under a license. If you do not know the terms of *
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* the license, please stop and do not read further. *
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* *
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****************************************************************/
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#include "mdef.h"
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#include "x86_64.h"
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#ifdef DEBUG
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void format_machine_inst(void);
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void initialize_registers(void);
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void reset_instruction(void);
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void print_source_operand(void);
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void print_destination_operand(void);
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void print_instruction(void);
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void set_memory_reg(void);
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void set_register_reg(void);
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void clear_memory_reg(void);
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#endif
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void emit_base_offset(int base, int offset);
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/* Define the COND values for use in the 2 byte JCC instructions.. */
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#define INST_SIZE 1
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#define XFER_BYTE_INST_SIZE 3
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#define XFER_LONG_INST_SIZE 6
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#define BRB_INST_SIZE 2
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#define JMP_LONG_INST_SIZE 5
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#define CALL_4LCLDO_XFER 2 /* index in ttt from start of call[sp] and forlcldo to xfer_table index */
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#define MAX_BRANCH_CODEGEN_SIZE 32 /* The length in bytes, of the longest form of branch instruction sequence */
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int x86_64_arg_reg(int indx);
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#define GET_ARG_REG(indx) x86_64_arg_reg(indx)
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/* Should be offset from RSP */
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#define STACK_ARG_OFFSET(indx) (8 * indx)
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enum condition
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{
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JO,
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JNO,
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JB,
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JC = JB,
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JNAE = JC,
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JNB,
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JNC = JNB,
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JAE = JNB,
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JZ,
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JE = JZ,
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JNZ,
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JNE = JNZ,
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JBE,
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JNA = JBE,
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JNBE,
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JA = JNBE,
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JS,
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JNS,
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JP,
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JPE = JP,
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JNP,
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JPO = JNP,
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JL,
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JNGE = JL,
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JNL,
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JGE = JNL,
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JLE,
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JNG = JLE,
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JNLE,
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JG = JNLE
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};
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#define REX_FIELD char
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#define REX_OP 0x40
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#define REX_B 0x01
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#define REX_X 0x02
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#define REX_R 0x04
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#define REX_W 0x08
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/* Note that while the register number we use in gtm can go from 0-15, the number of bits in the modrm/sib regfields are only 3.
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* So if we need to use the regs r8-r15, then a bit in the REX field should be set (depending on whether the register is encoded
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* in the sib or opcode or modrm, etc.
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*/
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#define SET_REX_PREFIX(REX_MANDATORY, REX_COND, reg) \
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{ \
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if (reg & 0x8) { /* If bit 3 (index starting from 0) is set, set the specified REX bit */ \
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emit_base_info.rex |= REX_COND; \
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} \
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emit_base_info.rex |= REX_OP | REX_MANDATORY; \
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emit_base_info.rex_set = 1; \
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}
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typedef union
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{
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ModR_M modrm;
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unsigned char byte;
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} modrm_byte_type;
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typedef union
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{
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SIB sib;
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unsigned char byte;
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} sib_byte_type;
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/* Instead of filling up the code buf, emit_base_offset will instead fill this structure, which will be used by the
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* macro which actually creates the instruction stream
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*/
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struct emit_base_info
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{
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REX_FIELD rex;
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modrm_byte_type modrm_byte;
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sib_byte_type sib_byte;
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char offset8;
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int offset32;
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int64_t offset64;
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char imm8;
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int imm32;
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int64_t imm64;
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int rex_set;
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int modrm_byte_set;
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int sib_byte_set; /* Not using bitfields, since this would generate faster code. Since this is a one-type only
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* created object, no real need for space optimization
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*/
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int offset8_set;
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int offset32_set;
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int offset64_set;
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int imm8_set;
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int imm32_set;
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int imm64_set;
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};
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GBLREF struct emit_base_info emit_base_info;
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/* Define the macros for the instructions to be generated.. */
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#define GENERIC_OPCODE_BEQ 1
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#define GENERIC_OPCODE_BGE 2
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#define GENERIC_OPCODE_BGT 3
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#define GENERIC_OPCODE_BLE 4
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#define GENERIC_OPCODE_BLT 5
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#define GENERIC_OPCODE_BNE 6
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#define GENERIC_OPCODE_BLBC 7
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#define GENERIC_OPCODE_BLBS 8
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#define GENERIC_OPCODE_BR 9
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#define GENERIC_OPCODE_LDA 11
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#define GENERIC_OPCODE_LOAD 12
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#define GENERIC_OPCODE_STORE 13
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#define GENERIC_OPCODE_STORE_ZERO 14
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#define GENERIC_OPCODE_NOP 15
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#define LONG_JUMP_OFFSET (0x7ffffffc)
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#define MAX_OFFSET 0xffffffff
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#define EMIT_JMP_ADJUST_BRANCH_OFFSET branch_offset -= 5
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#define EMIT_BASE_CODE_SIZE ((emit_base_info.rex_set ? 1 : 0) /* REX */ + 1 /* OPCODE */ + \
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(emit_base_info.modrm_byte_set ? 1 : 0) /* MODRM */ + \
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(emit_base_info.sib_byte_set ? 1 : 0) + (emit_base_info.offset8_set ? 1 : 0) + \
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(emit_base_info.offset32_set ? 4 : 0) + (emit_base_info.offset64_set ? 8 : 0) + \
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(emit_base_info.imm8_set ? 1 : 0) + (emit_base_info.imm32_set ? 4 : 0) + \
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(emit_base_info.imm64_set ? 8 : 0))
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#define CODE_BUF_GEN(op_code) \
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{ \
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(emit_base_info.rex_set) ? (code_buf[code_idx++] = emit_base_info.rex):0; \
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code_buf[code_idx++] = (char) op_code; \
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if (emit_base_info.modrm_byte_set) { \
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code_buf[code_idx++] = emit_base_info.modrm_byte.byte; \
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} \
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if (emit_base_info.sib_byte_set) { \
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code_buf[code_idx++] = emit_base_info.sib_byte.byte; \
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} \
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if (emit_base_info.offset8_set) { \
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code_buf[code_idx++] = emit_base_info.offset8; \
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} \
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if (emit_base_info.offset32_set) { \
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*((int4 *)&code_buf[code_idx]) = emit_base_info.offset32; \
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code_idx += SIZEOF(int4) ; \
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} \
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if (emit_base_info.offset64_set) { \
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*((int64_t *)&code_buf[code_idx]) = emit_base_info.offset64; \
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code_idx += SIZEOF(int64_t) ; \
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} \
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if (emit_base_info.imm8_set) { \
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code_buf[code_idx++] = emit_base_info.imm8; \
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} \
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if (emit_base_info.imm32_set) { \
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*((int4 *)&code_buf[code_idx]) = emit_base_info.imm32; \
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code_idx += SIZEOF(int4) ; \
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} \
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if (emit_base_info.imm64_set) { \
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*((int64_t *)&code_buf[code_idx]) = emit_base_info.imm64; \
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code_idx += SIZEOF(int64_t) ; \
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} \
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}
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#define IGEN_LOAD_WORD_REG_8(reg) \
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{ \
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SET_REX_PREFIX(REX_W, REX_R, reg) \
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
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CODE_BUF_GEN(I386_INS_MOV_Gv_Ev) \
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}
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#define IGEN_LOAD_NATIVE_REG(reg) IGEN_LOAD_WORD_REG_8(reg)
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/* Sign extended load */
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#define IGEN_LOAD_WORD_REG_4(reg) \
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{ \
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SET_REX_PREFIX(REX_W, REX_R, reg) \
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
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CODE_BUF_GEN(I386_INS_MOVSXD_Gv_Ev) \
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}
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#define IGEN_STORE_WORD_REG_8(reg) \
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{ \
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SET_REX_PREFIX(REX_W, REX_R, reg) \
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
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CODE_BUF_GEN(I386_INS_MOV_Ev_Gv) \
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}
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#define IGEN_STORE_WORD_REG_4(reg) \
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{ \
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SET_REX_PREFIX(0, REX_R, reg) \
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
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CODE_BUF_GEN(I386_INS_MOV_Ev_Gv) \
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}
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#define IGEN_STORE_ZERO_REG_8(reg) \
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{ \
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SET_REX_PREFIX(REX_W, 0, 0) \
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emit_base_info.imm32 = 0; \
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emit_base_info.imm32_set = 1; \
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CODE_BUF_GEN(I386_INS_MOV_Ev_Iv) \
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}
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#define IGEN_STORE_ZERO_REG_4(reg) \
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{ \
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emit_base_info.imm32 = 0; \
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emit_base_info.imm32_set = 1; \
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CODE_BUF_GEN(I386_INS_MOV_Ev_Iv) \
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}
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#define IGEN_GENERIC_REG(opcode, reg) \
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{\
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switch(opcode) \
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{\
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case GENERIC_OPCODE_LDA:\
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IGEN_LOAD_ADDR_REG(reg)\
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break;\
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case GENERIC_OPCODE_LOAD:\
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if ( next_ptr_offset == 4 ) { \
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IGEN_LOAD_WORD_REG_4(reg); \
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} else {\
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IGEN_LOAD_WORD_REG_8(reg); \
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} \
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next_ptr_offset = 8; \
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break;\
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case GENERIC_OPCODE_STORE:\
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if ( next_ptr_offset == 4 ) { \
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IGEN_STORE_WORD_REG_4(reg); \
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} else {\
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IGEN_STORE_WORD_REG_8(reg); \
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} \
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next_ptr_offset = 8; \
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break;\
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case GENERIC_OPCODE_STORE_ZERO:\
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if ( next_ptr_offset == 4 ) { \
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IGEN_STORE_ZERO_REG_4(reg); \
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} else {\
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IGEN_STORE_ZERO_REG_8(reg); \
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} \
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next_ptr_offset = 8; \
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break;\
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default: /* which opcode ? */ \
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GTMASSERT;\
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break;\
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}\
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}
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#define IGEN_LOAD_LINKAGE(reg) IGEN_LOAD_WORD_REG_8(reg)
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#define IGEN_LOAD_ADDR_REG(reg) \
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{ \
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SET_REX_PREFIX(REX_W, REX_R, reg) \
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
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CODE_BUF_GEN(I386_INS_LEA_Gv_M) \
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}
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#define GEN_STORE_ARG(reg, offset) \
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{ \
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X86_64_ONLY(force_32 = TRUE;) \
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GEN_STORE_WORD_8(reg, I386_REG_RSP, offset) \
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X86_64_ONLY(force_32 = FALSE;) \
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}
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#define GEN_LOAD_WORD_8(reg, base_reg, offset) \
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{ \
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emit_base_offset(base_reg, offset); \
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SET_REX_PREFIX(REX_W, REX_R, reg) \
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
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CODE_BUF_GEN(I386_INS_MOV_Gv_Ev) \
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}
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/* Load 4 bytes with sign extension */
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#define GEN_LOAD_WORD_4(reg, base_reg, offset) \
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{ \
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emit_base_offset(base_reg, offset); \
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SET_REX_PREFIX(REX_W, REX_R, reg) \
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
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CODE_BUF_GEN(I386_INS_MOVSXD_Gv_Ev) \
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}
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#define GEN_STORE_WORD_8(reg, base_reg, offset) \
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{ \
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emit_base_offset(base_reg, offset); \
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SET_REX_PREFIX(REX_W, REX_R, reg) \
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
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CODE_BUF_GEN(I386_INS_MOV_Ev_Gv) \
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}
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#define GEN_STORE_WORD_4(reg, base_reg, offset) \
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{ \
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emit_base_offset(base_reg, offset); \
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SET_REX_PREFIX(0, REX_R, reg) \
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
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CODE_BUF_GEN(I386_INS_MOV_Ev_Gv) \
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}
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#define GEN_LOAD_IMMED(reg, imval) \
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{ \
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int op_code = I386_INS_MOV_eAX + (reg & 0x7); \
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memset((void *)&emit_base_info, 0, SIZEOF(emit_base_info)); \
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SET_REX_PREFIX(0, REX_B, reg) \
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emit_base_info.imm32 = (int) imval & 0xffffffff; \
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emit_base_info.imm32_set = 1; \
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CODE_BUF_GEN(op_code) \
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}
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#define GEN_CLEAR_WORD_EMIT(reg) emit_trip(*(fst_opr + *inst++), TRUE, GENERIC_OPCODE_STORE_ZERO, reg)
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#define GEN_LOAD_WORD_EMIT(reg) emit_trip(*(fst_opr + *inst++), TRUE, GENERIC_OPCODE_LOAD, reg)
|
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|
||
|
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#define EMIT_TRIP_ILIT_GEN GEN_LOAD_IMMED(trg_reg, immediate)
|
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|
||
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#define GEN_XFER_TBL_CALL(xfer) \
|
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|
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{ \
|
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emit_base_offset(GTM_REG_XFER_TABLE, xfer); \
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emit_base_info.rex_set = 0; \
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assert(GTM_REG_XFER_TABLE <= 7); /* if its a 64 bit register, we might need to set the REX bit */ \
|
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emit_base_info.modrm_byte.modrm.reg_opcode = (char) I386_INS_CALL_Ev; \
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CODE_BUF_GEN(I386_INS_Grp5_Prefix) \
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|
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}
|
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|
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|
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#define GEN_CMP_EAX_IMM32(imm) \
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|
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{ \
|
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int op_code = I386_INS_CMP_eAX_Iv ; \
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memset((void *)&emit_base_info, 0, SIZEOF(emit_base_info)); \
|
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|
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emit_base_info.imm32 = (int4) imm & 0xffffffff; \
|
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emit_base_info.imm32_set = 1; \
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CODE_BUF_GEN(op_code) \
|
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|
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}
|
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|
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|
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|
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|
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#define GEN_CMP_MEM64_ZERO(base_reg, offset) \
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|
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{ \
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int op_code = I386_INS_Grp1_Ev_Iv_Prefix; \
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|
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emit_base_offset(base_reg, offset); \
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|
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SET_REX_PREFIX(REX_W, 0, 0) \
|
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|
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emit_base_info.modrm_byte.modrm.reg_opcode = I386_INS_CMP__; \
|
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|
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emit_base_info.imm32 = (int4) 0; \
|
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|
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emit_base_info.imm32_set = 1; \
|
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|
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CODE_BUF_GEN(op_code) \
|
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|
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}
|
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|
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|
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#define GEN_CMP_MEM32_ZERO(base_reg, offset) \
|
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|
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{ \
|
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|
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int op_code = I386_INS_Grp1_Ev_Iv_Prefix; \
|
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|
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emit_base_offset(base_reg, offset); \
|
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|
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emit_base_info.modrm_byte.modrm.reg_opcode = I386_INS_CMP__; \
|
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|
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emit_base_info.imm32 = (int4) 0 ; \
|
||
|
|
emit_base_info.imm32_set = 1; \
|
||
|
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CODE_BUF_GEN(op_code) \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define GEN_CMP_REG_MEM32(reg, base_reg, offset) \
|
||
|
|
{ \
|
||
|
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int op_code = I386_INS_CMP_Gv_Ev; \
|
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|
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emit_base_offset(base_reg, offset); \
|
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|
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SET_REX_PREFIX(0, REX_R, reg) \
|
||
|
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emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
|
||
|
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CODE_BUF_GEN(op_code) \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define GEN_CMP_REG_MEM64(reg, base_reg, offset) \
|
||
|
|
{ \
|
||
|
|
int op_code = I386_INS_CMP_Gv_Ev; \
|
||
|
|
emit_base_offset(base_reg, offset); \
|
||
|
|
SET_REX_PREFIX(REX_W, REX_R, reg) \
|
||
|
|
emit_base_info.modrm_byte.modrm.reg_opcode = reg & 0x7; \
|
||
|
|
CODE_BUF_GEN(op_code) \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define GEN_CMP_REGS(reg1, reg2) \
|
||
|
|
{ \
|
||
|
|
int op_code = I386_INS_CMP_Gv_Ev; \
|
||
|
|
memset((void *)&emit_base_info, 0, SIZEOF(emit_base_info)); \
|
||
|
|
SET_REX_PREFIX(REX_W, REX_R, reg1) \
|
||
|
|
SET_REX_PREFIX(0, REX_B, reg2) \
|
||
|
|
emit_base_info.modrm_byte.modrm.reg_opcode = reg1 & 0x7; \
|
||
|
|
emit_base_info.modrm_byte.modrm.mod = I386_MOD32_REGISTER; \
|
||
|
|
emit_base_info.modrm_byte.modrm.r_m = reg2 & 0x7; \
|
||
|
|
emit_base_info.modrm_byte_set = 1; \
|
||
|
|
CODE_BUF_GEN(op_code) \
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Note that there is no CMP_IMM64 in AMD64 */
|
||
|
|
#define GEN_CMP_IMM32(reg, imm) \
|
||
|
|
{ \
|
||
|
|
int op_code = I386_INS_Grp1_Ev_Iv_Prefix; \
|
||
|
|
memset((void *)&emit_base_info, 0, SIZEOF(emit_base_info)); \
|
||
|
|
emit_base_info.modrm_byte.modrm.reg_opcode = I386_INS_CMP__; \
|
||
|
|
emit_base_info.modrm_byte.modrm.mod = I386_MOD32_REGISTER; \
|
||
|
|
emit_base_info.modrm_byte.modrm.r_m = reg & 0x7; \
|
||
|
|
emit_base_info.modrm_byte_set = 1; \
|
||
|
|
SET_REX_PREFIX(0, REX_B, reg) \
|
||
|
|
emit_base_info.imm32 = (int4) imm & 0xffffffff; \
|
||
|
|
emit_base_info.imm32_set = 1; \
|
||
|
|
CODE_BUF_GEN(op_code) \
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#define GEN_SUBTRACT_REGS(src1, src2, trgt) GTMASSERT;
|
||
|
|
|
||
|
|
#define GEN_ADD_IMMED(reg, imval) \
|
||
|
|
{ \
|
||
|
|
int op_code = I386_INS_Grp1_Ev_Iv_Prefix; \
|
||
|
|
memset((void *)&emit_base_info, 0, SIZEOF(emit_base_info)); \
|
||
|
|
SET_REX_PREFIX(REX_W, REX_B, reg) \
|
||
|
|
emit_base_info.modrm_byte_set = 1; \
|
||
|
|
emit_base_info.modrm_byte.modrm.mod = I386_MOD32_REGISTER; \
|
||
|
|
emit_base_info.modrm_byte.modrm.reg_opcode = I386_INS_ADD__; \
|
||
|
|
emit_base_info.modrm_byte.modrm.r_m = reg & 0x7; \
|
||
|
|
emit_base_info.imm32 = (int4) imval; \
|
||
|
|
emit_base_info.imm32_set = 1; \
|
||
|
|
CODE_BUF_GEN(op_code) \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define GEN_MOVE_REG(trg, src) \
|
||
|
|
{ \
|
||
|
|
int op_code = I386_INS_MOV_Ev_Gv; \
|
||
|
|
memset((void *)&emit_base_info, 0, SIZEOF(emit_base_info)); \
|
||
|
|
SET_REX_PREFIX(REX_W, REX_B, trg) \
|
||
|
|
SET_REX_PREFIX(0, REX_R, src) \
|
||
|
|
emit_base_info.modrm_byte_set = 1; \
|
||
|
|
emit_base_info.modrm_byte.modrm.mod = I386_MOD32_REGISTER; \
|
||
|
|
emit_base_info.modrm_byte.modrm.reg_opcode = src; \
|
||
|
|
emit_base_info.modrm_byte.modrm.r_m = trg & 0x7; \
|
||
|
|
CODE_BUF_GEN(op_code) \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define GEN_JUMP_REG(reg) \
|
||
|
|
{ \
|
||
|
|
int op_code = I386_INS_Grp5_Prefix; \
|
||
|
|
memset((void *)&emit_base_info, 0, SIZEOF(emit_base_info)); \
|
||
|
|
SET_REX_PREFIX(REX_OP | REX_W, REX_B, reg) \
|
||
|
|
emit_base_info.modrm_byte_set = 1; \
|
||
|
|
emit_base_info.modrm_byte.modrm.mod = I386_MOD32_REGISTER; \
|
||
|
|
emit_base_info.modrm_byte.modrm.reg_opcode = I386_INS_JMP_Ev; \
|
||
|
|
emit_base_info.modrm_byte.modrm.r_m = reg & 0x7; \
|
||
|
|
CODE_BUF_GEN(op_code) \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define GEN_PCREL \
|
||
|
|
{ \
|
||
|
|
int op_code = I386_INS_CALL_Jv; \
|
||
|
|
memset((void *)&emit_base_info, 0, SIZEOF(emit_base_info)); \
|
||
|
|
emit_base_info.imm32 = 0; \
|
||
|
|
emit_base_info.imm32_set = 1; \
|
||
|
|
CODE_BUF_GEN(op_code) \
|
||
|
|
memset((void *)&emit_base_info, 0, SIZEOF(emit_base_info)); \
|
||
|
|
op_code = I386_INS_POP_eAX + (GTM_REG_CODEGEN_TEMP & 0x7); \
|
||
|
|
SET_REX_PREFIX(0, REX_B, GTM_REG_CODEGEN_TEMP) \
|
||
|
|
assert(GTM_REG_CODEGEN_TEMP > 7); \
|
||
|
|
CODE_BUF_GEN(op_code) \
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GT.M on AIX and SPARC is 64bit
|
||
|
|
* By default the loads/stores use ldd/std(load double),
|
||
|
|
* but if the value being dealt with is a word,the
|
||
|
|
* opcode in generic_inst is changed to ldw/stw
|
||
|
|
* On other platforms, it is defined to null
|
||
|
|
*/
|
||
|
|
#define REVERT_GENERICINST_TO_WORD(inst)
|